An error condition exists at the interface of two systems of synchronous logic with dissimilar and asynchronous clocking rates because of what is commonly referred to as the metastable latch problem. In a bistable latch where the coincidental occurrence of two pulses is required to change the state of the latch, an anomalous failure mode occurs when the two actuating pulses do not overlap sufficiently to cause the latch to completely switch from one of its stable states to the other. With such insufficient overlap of the two actuating pulses, the output or outputs of the latch do not go to either one of the stable up or down levels but actually perturbate at or around a third level referred to as the metastable level. The metastable level is exactly half way between the up and down levels, and when metastability occurs, the latch outputs either momentarily sit at the metastable level before randomly changing to a stable up or down level or alternatively they oscillate around this metastable level.
In latches actuated by signals from two different logic systems running under different and asynchronous clocking rates, the metastable latch problem arises because the clock pulse of one of the systems overlaps, captures or samples an insufficient portion of the data signal from the other system. It is particularly difficult to correct metastability in the transfer of data between two asychronous systems because the phase of the data signals of each of the two systems is continuously changing with respect to the clock pulses of the other system.
As far as it is caused by differences in clocking rates the metastable latch problem can be solved with known techniques, by running both interfacing systems, from a single clock or two synchronized clocks, at the same clocking rate or at harmonically related clocking rates. However, using the same clocking rate or a harmonic relationship between the two clocking rates is not always a practical solution in any given situation, since it may not allow either system to run anywhere near its optimum operating rate. What is needed is a relationship between the two clocking rates that would allow each of the interfacing systems to approach its maximum performance level while providing the reliable sampling of intersystem logic states.